A Reactive System-specific Compilation Chain from Synchronous Dataflow Models to FPGA Netlist
Résumé
Modern Field Programmable Gate Arrays (FPGAs)
offer a solution to several issues related to real-time on-board
systems, such as guaranteed execution time. They are currently
considered as target platforms for space applications. However, the complexity of producing circuits on these components
poses a challenge to their widespread adoption. To address
this issue, high-level synthesis tools provide another layer of
abstraction above the logic circuit design process, for example
compiling C code into Hardware Description Languages such
as VHDL or Verilog. However, high-level synthesis results are
poorly predictable and do not guarantee the efficient use of
recent FPGA capabilities provided by new primitives like digital
signal processor or random-access memory. In this paper we
propose a compilation chain dedicated to reactive systems, ie.
controllers, providing a more predictable synthesis process for
critical embedded control applications. The implemented solution
demonstrates timing performance equivalent to the traditional
synthesis process with a more predictable result.
Origine : Fichiers produits par l'(les) auteur(s)
Licence : CC BY - Paternité
Licence : CC BY - Paternité
